“xbus_response” and “xbus_request” are packed structs import “DPI” function response send_packet(request req) Ģ. The DPI enables direct calling of SC functions in the SV testbench code. The SV Direct Programming Interface (DPI) can be used for connecting an SV testbench to SC method ports.
xbus_response send_packet(xbus_request & req) Here is an example of a method in a SC model that is used for sending a packet:ģ. SystemC models define the methods the testbench must communicate with. For the data type communication, the values from the type in one language are mapped to an appropriate type in the other language.ī. Using this Verilog shell for SC, the SV testbench can communicate to any of the SC ports. The data types in both languages must match. The foreign attribute string value in line number 3 must be SystemC. Module name must match exactly the name ofģ.
This shell defines the ports whose name and type match the SystemC ports. Taking an example of SV with SC, a Verilog shell module must be defined for the purpose of instantiating the SC module (this shell can also be automatically generated by tools or scripts for example ncsc_run from Cadence generates it during compilation).
A DUT TLM written in SystemC must be connected to a testbench written in SV or e or any other verification language.įollowing is a simple example of a SystemC signal declaration in the TLM. Port/signal connectivity is required between the verification environment and the DUT for driving or monitoring or both. Here's an excerpt from a paper that will be delivered by Leena Singh at DVCon next month:Ī.
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